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0-In Boosts Efficiency of Coverage-Driven Verification with Structural Coverage and Formal Analysis
Archer Verification(TM) System Version 2.2 Helps Users Find
and Fill Coverage Holes in the Total Coverage Model to
More Rapidly Reach Verification Closure
SAN JOSE, Calif.—(BUSINESS WIRE)—May 17, 2004—
Today 0-In Design Automation, the Assertion-Based Verification
Company, announced version 2.2 of its Archer Verification(TM) system,
which continues the 0-In tradition of combining the best tools with
the best engineered methodologies. Version 2.2 improves the efficiency
of coverage-driven verification (CDV) methodologies, enabling
productivity improvements for design and verification teams working on
multi-million gate system-on-chip (SoC) and ASIC designs. These
enhancements to the Archer Verification system allow users to more
accurately measure total coverage of a design, including functional,
transactional and structural coverage, and to understand how to reach
coverage closure.
The Archer Verification system (version 2.2) has been upgraded
with the following features:
-- Upgraded coverage reporting and analysis of transaction and
structural coverage.
-- Enhanced assertion synthesis capability to automatically
generate pre-condition coverage monitoring and reporting for
Property Specification Language (PSL) assertions.
-- Enhanced assertion synthesis capability to automatically
generate structural coverage monitoring and reporting for the
Open Verification Library (OVL) set of assertion checkers.
-- Ability to target coverage points with exhaustive formal
analysis to find sequential inputs needed to exercise corner
case behaviors.
-- Integration with Verisity's Specman Elite(R) coverage
capabilities to report and analyze structural coverage
combined with functional coverage.
"Our focus is on delivering best practices for applying advanced
technologies in easy-to-use, high-value solutions," said Steve White,
president and CEO of 0-In. "The Archer Verification system leverages
and integrates with today's methodologies to help our customers find
more bugs faster. Assertions and formal verification provide critical
capabilities that boost the efficiency of coverage-driven simulation
today by improving both observability and controllability,"
Highlight Transaction Coverage and Corner Cases Efficiently
Archer-CDV version 2.2 includes enhanced coverage reporting and
analysis of transaction and structural coverage from simulation that
allows users to quickly understand the types of transactions and
corner cases exercised by simulation. In particular, users can rapidly
identify "coverage holes" in their environment -- verification
scenarios that were not exercised but represent significant
functionality or important test cases.
Archer-CDV leverages the structural coverage information that is
included automatically with the CheckerWare(R) library of assertion
checkers. This industry-leading library of functional verification
checkers makes users more productive by simplifying the specification
of both functional checking assertions and structural coverage
monitoring in a single encapsulated element. The CheckerWare library
consists of standard interface and protocol monitors, high-level
functionality checkers and low-level register-transfer level (RTL)
structural checkers.
Measure Coverage for Open Standards
The assertion synthesis capability of Archer-CDV also has been
enhanced to provide assertion and structural coverage information for
standard assertion formats, including PSL and OVL. For PSL,
pre-conditions of an assertion are monitored for activation and
coverage reports generated. This allows users to understand the extent
of checking performed by their PSL assertions.
For OVL, the assertion synthesis capability of Archer-CDV now
provides structural coverage monitors for elements based on the
corresponding CheckerWare element (which has built-in structural
coverage). This allows OVL users to obtain implementation-specific
corner case monitoring. For example, in the assert_win_change checker,
coverage monitoring logic is created to detect whether events have
occurred at the start and end times of the time window specified in
the assertion.
Target Coverage Holes with Formal Analysis
Archer-ABV (the full assertion-based verification product that
includes static and dynamic formal verification) has been enhanced in
version 2.2 to target simulation coverage points using exhaustive
formal analysis. One of the most difficult tasks in a coverage-driven
verification methodology is discovering how to fill coverage holes
identified by coverage measurements. Because coverage holes are
frequently difficult to exercise, verification requires a complex
combination of input sequences and precise timing of events. In other
cases, coverage points are impossible to stimulate with legal inputs,
so manual analysis is simply wasted looking for a non-existent
sequence.
With the target coverage feature of Archer-ABV, exhaustive formal
analysis can be applied to directly find sequences of legal inputs
that can exercise coverage points. The formal analysis also can find
and report on coverage points that can never be reached with legal
input sequences.
This feature fills a critical gap in current CDV methodologies -
how to reach unexercised coverage points efficiently. Until now, this
usually involved difficult manual crafting of complex test scenarios
or extremely long and open-ended pseudo-random simulations. With
Archer-ABV, users can quickly apply computing power to find and report
the critical input sequence in simulation. This industry-leading
capability is enabled by Archer-ABV's unique ability to guarantee that
formal analysis results will match simulation at all times.
Integrate Structural Coverage with Verisity's VPA Solutions
Archer Verification version 2.2 also contains the ability to
combine structural coverage information with functional coverage
information in Verisity's VPA solutions, including the SpeXsim(TM)
verification system and Specman Elite(R). This is achieved through an
integration with Verisity's Coverage and Assertion Interface (CAI).
The information that is provided to the SpeXsim and Specman Elite
coverage tools includes structural coverage from CheckerWare and OVL,
transaction information in CheckerWare monitors and assertion coverage
information for PSL. The coverage information can be used for total
coverage management using reporting, analysis, and simulation ranking
tools.
Pricing and Availability
Version 2.2 of the Archer Verification system will be demonstrated
in Booth #3243 at the Design Automation Conference (DAC) in San Diego,
June 7 - 11, and will ship to customers starting in June, 2004. North
American list prices remain unchanged for all components of the
system: Archer-CDV $50,000; Archer-SF $60,000; and Archer-ABV
$120,000.
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and
supports functional verification products that help verify
multi-million gate application-specific integrated circuit (ASIC) and
system-on-chip (SoC) designs. The company delivers a comprehensive
assertion-based verification (ABV) solution built on industry
standards that provides value throughout the design and verification
cycle - from the block level to the chip and system levels. Twelve of
the 15 largest electronics companies have adopted 0-In tools and
methodologies in their integrated circuit (IC) design verification
flows. 0-In was founded in 1996 and is based in San Jose, Calif. For
more information, see http://www.0-in.com.
0-In(R) and CheckerWare(R) and Archer Verification(TM) are
trademarks or registered trademarks of 0-In Design Automation, Inc.
All other trademarks are the property of their respective holders.
Contact:
0-In Design Automation
Richard Ho, 408-487-3647
richard@0-in.com
or
Cayenne Communication for 0-In Design Automation
Linda Marchant, 919-683-9545
linda.marchant@cayennecom.com
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